module Control(clk, reset, InstructionOPCode, 
                Branch, MemRead, MemtoReg, ALUop, MemWrite, ALUSrc, RegWrite);

    input wire[6:0] InstructionOPCode;
    input wire reset;
    input wire clk;

    output reg Branch;  //分支指令信号
    output reg MemRead;  //读内存信号（load）
    output reg MemtoReg;    //多路选择器控制信号（内存数还是ALUresult）
    output reg[1:0] ALUop;   //ALU控制信号
    output reg MemWrite;    //写内存信号
    output reg ALUSrc;      //多路选择器控制信号（操作数还是立即数）
    output reg RegWrite;    //允许写入寄存器信号

    parameter addOPCode = 7'd1;
    parameter subOPCode = 7'd2;
    parameter andOPCode = 7'd3;
    parameter orOPCode = 7'd4;
    parameter beqOPCode = 7'd5;
    parameter ldOPCode = 7'd6;
    parameter sdOPCode = 7'd7;



    // always @(posedge reset)
    // begin
    //     Branch = 0;
    //     MemRead = 0;
    //     MemtoReg = 0;
    //     ALUop = 2'b11;
    //     MemWrite = 0;
    //     ALUSrc = 0;
    //     RegWrite = 0;
    // end

    always @(InstructionOPCode)
    begin
        case (InstructionOPCode)
            addOPCode:
            begin
                RegWrite <= 1;
                ALUSrc <= 0;  //ALUSrc=0 choose readdata2
                MemWrite <= 0;
                ALUop <= 2'b10;
                MemtoReg <= 0; //MemtoReg means data writing to regs is from ALU result.
                MemRead <= 0;
                Branch <= 0; 
            end 
            subOPCode:
            begin
                RegWrite <= 1;
                ALUSrc <= 0;  //ALUSrc=0 choose readdata2
                MemWrite <= 0;
                ALUop <= 2'b10;
                MemtoReg <= 0; //MemtoReg means data writing to regs is from ALU result.
                MemRead <= 0;
                Branch <= 0; 
            end
            andOPCode:
            begin
                RegWrite <= 1;
                ALUSrc <= 0;  //ALUSrc=0 choose readdata2
                MemWrite <= 0;
                ALUop <= 2'b10;
                MemtoReg <= 0; //MemtoReg means data writing to regs is from ALU result.
                MemRead <= 0;
                Branch <= 0; 
            end
            orOPCode:
            begin
                RegWrite <= 1;
                ALUSrc <= 0;  //ALUSrc=0 choose readdata2
                MemWrite <= 0;
                ALUop <= 2'b10;
                MemtoReg <= 0; //MemtoReg means data writing to regs is from ALU result.
                MemRead <= 0;
                Branch <= 0; 
            end
            beqOPCode:
            begin
                RegWrite <= 0;
                ALUSrc <= 0;  //ALUSrc=0 choose readdata2
                MemWrite <= 0;
                ALUop <= 2'b01;
                MemRead <= 0;
                Branch <= 1; 
            end
            ldOPCode:
            begin
                RegWrite <= 1;
                ALUSrc <= 1;  //ALUSrc=1 choose imm
                MemWrite <= 0;
                ALUop <= 2'b00;
                MemtoReg <= 1; //MemtoReg=1 means data writing to regs is from Mem.
                MemRead <= 1;
                Branch <= 0; 
            end
            sdOPCode:
            begin
                RegWrite <= 0;
                ALUSrc <= 1;  //ALUSrc=1 choose imm
                MemWrite <= 1;
                ALUop <= 2'b00;
                MemtoReg <= 0; //MemtoReg=1 means data writing to regs is from Mem.
                MemRead <= 0;
                Branch <= 0; 
            end
        endcase
    end

endmodule